Principal Digital Design Engineer, Santa Clara

Principal Digital Design Engineer

New Yesterday

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com

Job Description: As a Digital Designer in the DSP SerDes team, you will join a pivotal project to develop advanced high speed SerDes wireline and optical transceivers for AI systems.

Basic Qualifications:

Hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
5-10 years of experience in digital design for high-speed DSP data path.
Be proficient in coding System Verilog for complex design blocks.
Have experience with EDA tools for Synthesis, Lint, CDC, and Prime Time.
Have experience taking design blocks through the full design cycle, from micro-architecture to tapeout.
Have experience with timing fixes, area and power optimizations, and resolving silicon issues.

Required Experience:

Serve as the responsible engineer for at least one critical design block, including architecture definition, design specifications, and RTL delivery.
Code and deliver high-quality RTL to the PD and DV teams.
Collaborate with the DSP Architecture team to define new features and suggest optimizations for power, latency, and performance.
Work with the PD team to resolve timing violations, Spyglass warnings/errors, and CDC violations.
Partner with the DV team to root-cause and fix design bugs.

Preferred Experience:

Experience in digital design for high speed data path in 100G+ PAM4 DSP SerDes
Experience in designing PAM4 DSP blocks for FFE, DFE, MLSD, and digital timing recovery.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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Location:: Santa Clara

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