Principal Design Engineer

New Today

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell Custom Solutions develops cutting-edge solutions for large AI, cloud data center, and telecom customers. The SoCs encompass best-in-class performance, advanced die-to-die and packaging technology, and optimized low-power techniques. As part of the Marvell Data Center RTL Design Team, you will help shape the micro-architecture of the blocks, cores, accelerators and subsystems that make up an SoC. You will work closely with architecture, floorplanning, verification, DFT, STA and other teams to design and implement world-class hardware, making a significant impact for the company and our renowned customers who are leaders in their respective domains.

What You Can Expect
•Own and debug failures in simulation to root-cause problems •Work closely with Physical Design team for floorplanning, timing, power and area optimization. •Work closely with verification team for test plan development, debug, coverage closure and gate level simulations •Coach and mentor junior engineers of the team when necessary to achieve successful project outcomes.

What We're Looking For

Bachelor's degree in Computer Science, Electrical Engineering or related fields and 7+ years of related professional experience. OR Master's degree in Computer Science, Electrical Engineering or related fields with 4+ years of experience. •Experience with general digital design microarchitecture development. •Design/RTL experience in Verilog or SystemVerilog. •Knowledge of scripting languages, such as PERL, Python •Experience with high speed, low power, and area optimized designs. •Experience working with multi-clock designs, DFT, resets, LEC, Lint, etc. •Good learning, problem solving interpersonal and communication skills. •Must be a team player with a strong can-do attitude. •Self-motivated team player able to thrive in a fast-paced engineering environment.

Expected Base Pay Range (USD)
146,850 - 220,000, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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Location:
Santa Clara

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