Technical Lead Design Verification Engineer San Jose, CA

Below covers everything you need to know about what this opportunity entails, as well as what is expected from applicants. Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . We are looking for Senior Design Verification Engineers with a flair for being a code breaker and the ability to develop hybrid verification mechanisms for complex ASICs. Experience with SystemVerilog, C, C++, Python, or other scripting languages is a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full verification lifecycle, from planning to writing tests, debugging, collecting, and closing coverage. You will also collaborate with software and system validation teams to develop and execute test plans on emulation platforms. Strong academic and technical background in electrical engineering. A minimum of a Bachelor’s in EE is required, and a Master’s is preferred. ≥5 years’ experience verifying and validating complex SoCs for Server, Storage, and Networking applications. Knowledge of industry-standard simulators, revision control systems, and regression systems. Professional attitude with the ability to prioritize multiple tasks and work independently with minimal guidance. Entrepreneurial, open-minded, and proactive attitude, with a focus on customer needs. Authorized to work in the US and available to start immediately. Required Experience Experience with the full verification lifecycle using SystemVerilog, UVM, C, C++. Proven ability to deploy hybrid verification techniques, including directed and constrained random testing. Experience with bug hunting and coverage analysis; formal methods experience is a plus. Ability to independently develop test plans and sequences, and collaborate with RTL designers to debug failures. Ability to define and implement coverage measures for stimuli and corner cases, ensuring comprehensive verification coverage. Preferred Experience Experience scripting with Perl or Python to automate verification infrastructure. Experience working with third-party Verification IPs for protocols like PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc. Experience with directed testing methodologies, cache verification, and formal verification methods. The base salary range is USD 147,000.00 – USD 195,000.00. Salary will be determined based on location, experience, and internal pay scales. We value diversity and inclusion and encourage applicants from all backgrounds, including people of color, LGBTQ+ and non-binary individuals, veterans, parents, and persons with disabilities, to apply. Apply for this job * indicates a required field First Name * Last Name * Preferred First Name Email * Phone Resume/CV Enter manually or upload file (pdf, doc, docx, txt, rtf) LinkedIn Profile Website Years of relevant full-time experience? Willing to relocate? If yes, to which location(s)? * I have reviewed and consented to the privacy policies. *

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