STA Lead Application Engineer

New Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities; Perform Static timing analysis, glitch, noise analysis using Tempus Signoff tool. Executing and delivering on various aspects of Timing analysis flows, ECO flows, CAD tools and methodologies.
·Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. ·Work efficiently with R&D and customer to enable various timing analysis & ECO flows including newer advanced technologies. ·Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. ·Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction and UPF/CPF concepts.
·Execute and lead Tempus timing signoff campaigns at existing and new customers. ·Automation of flows using scripting languages (Perl, Tcl, python).
·Deliver technical trainings and seminars within Cadence and customer sites. Requirements; 3+ years of experience in Static timing analysis, Individual should be able to lead and execute technical campaigns at various internal and external customers. Perform several timing & correlation benchmarks with Cadence Tempus -Signoff tool. Execute and deliver on timing analysis & ECO flows and ensure integrity of delivered solutions. Individual should be able to efficiently work with Cadence R&D to enable various tool feature and close tool bug fixes. Work on various aspects of physical design including timing analysis, place and route, extraction, spice etc. We’re doing work that matters. Help us solve what others can’t.
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Location:
San Jose

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