SoC Physical Design Engineer

New Yesterday

Summary: Meta's Reality Labs(RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.As an SoC Physical Design Engineer at Meta Reality Labs, you will perform physical design implementation of complex SoC and IP-subsystems. In this high impact role, you will work closely with cross functional teams to ensure our custom silicon developments meet the challenging power, performance and area requirements needed for our wearable products. Required Skills: SoC Physical Design Engineer Responsibilities: Physical design implementation from RTL to netlist for complex digital blocks or full-chip designs, responsible for floorplanning, placement, clock tree synthesis (CTS), routing, static timing analysis and signoff
Collaborate with RTL design, DFT, verification, and power teams to ensure seamless integration and secure QOR
Optimize for power, performance, and area (PPA) using industry-standard tools and methodologies
Contribute to automation of physical design flows and improve design productivity
Minimum Qualifications: Minimum Qualifications: Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
3+ years of hands-on experience in ASIC physical design with solid understanding of digital design fundamentals
Proficient in using industry-standard EDA tools such as Synopsys (ICC2, Fusion Compiler, PrimeTime), Cadence (Innovus), or Mentor (Calibre)
Fluent in scripting languages such as TCL, Perl, or Python for flow automation
Experienced in cross-functional communication and collaboration
Preferred Qualifications: Preferred Qualifications: Experience with low-power design techniques
Proficient in STA, clock tree synthesis and IR drop analysis
Knowledge of MBIST, Scan implementation and tradeoffs for physical convergence
Experience with advanced process nodes (7nm or below)
Public Compensation: $114,000/year to $166,000/year + bonus + equity + benefits Industry: Internet Equal Opportunity: Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.
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Location:
Sunnyvale, CA, United States
Salary:
$200,000 - $250,000
Category:
Engineering

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