SoC Physical Design Engineer, STA/Timing Waltham, Massachusetts, United States | Hardware

Please read the information in this job post thoroughly to understand exactly what is expected of potential candidates. Description - Collaborate with design teams to understand and debug constraints, facilitating logic changes to optimize timing. - Work with the Physical Design team to identify issues and share best practices. - Develop and implement timing ECOs for project tapeouts. - Create and maintain scripts and methodologies for analysis and runs. - Document processes and contribute to guidelines and specifications. - Conduct detailed analysis of timing paths to identify key issues. - Implement timing infrastructure to support design goals. Minimum Qualifications Bachelor's degree and 3+ years of relevant industry experience. Experience with large design STA and timing closure. Proficiency in programming with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Knowledge of timing aspects in large high-performance SoC designs in sub-micron technologies. Understanding of timing closure methodologies, noise, crosstalk, and OCV effects. Familiarity with circuit modeling, including SPICE models and corner analysis. Experience with ECO techniques and implementation. Strong communication skills to clearly describe issues and follow through to resolution.

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