Senior Physical Design Engineer, Google CloudSenior Physical Design Engineer, Google Cloud 5 days ago Be among the first 25 applicants Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience in static timing analysis. Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs. Experience in PrimeTime or Tempus TCL scripting and static timing analysis debug.

The full job description covers all associated skills, previous experience, and any qualifications that applicants are expected to have.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience in static timing analysis. Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs. Experience in PrimeTime or Tempus TCL scripting and static timing analysis debug.

Preferred qualifications:

Experience writing, reviewing and verifying complex TCL constraints for static timing analysis. Experience in extraction of design parameters, QoR metrics, and analyzing data trends. Experience working with multiple foundries. Knowledge of semiconductor device physics and transistor characteristics.

About The Job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will work on the physical implementation of Application-specific Integrated Circuits (ASIC) using advanced technology nodes. You will work on timing margin derivation, constraint development and validation, and timing closure of large, complex high-performance compute ASICs. You will develop static timing methodologies, margins, automation scripts, and write documentation. You will perform technical evaluations of vendors, tools, methodologies, and will provide recommendations. Additionally, you will work with architecture, logic design, and Design for testing (DFT) teams to understand and implement their requirements.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

Debug and resolve common Static Timing Analysis (STA) or design rule issues like unconstrained endpoints, maximum transition, minimum period, or minimum pulse width violations. Perform full chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs. Utilize Perl, Python, TCL, or Bash to create static timing flow automation scripts. Own and maintain primetime STA flows.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.Seniority level Seniority levelMid-Senior level Employment type Employment typeFull-time Job function Job functionOther, Information Technology, and Engineering IndustriesInformation Services and Technology, Information and Internet Referrals increase your chances of interviewing at Google by 2x Get notified about new Senior Physical Design Engineer jobs in Sunnyvale, CA . San Jose, CA $175,000.00-$255,000.00 3 weeks ago Senior Mechanical Engineer – Interconnect Design San Jose, CA $200,000.00-$300,000.00 6 days ago Senior Quality Engineer (Design Control & Risk Management) Sunnyvale, CA $126,100.00-$213,500.00 1 week ago Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration teamSenior Quality Engineer (Design Controls and V&V) Sunnyvale, CA $126,100.00-$213,500.00 1 week ago Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration teamSenior Quality Engineer (Design Control and Risk Management) Sunnyvale, CA $126,100.00-$213,500.00 1 week ago San Jose, CA $175,000.00-$225,000.00 2 weeks ago Mountain View, CA $183,000.00-$271,000.00 1 week ago Physical Design Engineer, Custom Datapath Sunnyvale, CA $183,000.00-$271,000.00 2 weeks ago San Jose, CA $150,000.00-$275,000.00 6 days ago Sunnyvale, CA $142,000.00-$203,000.00 3 weeks ago Sr. Physical Design Engineer, Annapurna Labs Cupertino, CA $143,300.00-$247,600.00 3 weeks ago Physical Design and Verification EngineerSr. Physical Design Engineer, Annapurna LabsSenior Physical Design Applications Engineer Returnship San Jose, CA $59,500.00-$110,500.00 1 day ago Senior Physical Design Methodology Engineer San Francisco Bay Area $145,000.00-$225,000.00 4 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

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