Piper Companies is seeking a Principal IC Packaging Engineer who will develop and refine Chip-on-Wafer-on-Substrate technology. The Packaging engineer will be onsite 5 days a week in Saratoga, CA. Requirements for the IC Packaging Engineer include: -Innovate and enhance CoWoS packaging processes to boost chip performance, power efficiency, and reliability. -Collaborate with design, test, and manufacturing teams to ensure flawless chip-package integration. -Lead failure analysis and drive yield improvements across packaging processes. -Ensure CoWoS packaging meets all thermal, mechanical, and electrical performance standards. -Support new product introduction (NPI) from initial prototyping to high-volume manufacturing. -Partner with foundry and OSAT partners (e.g., TSMC, ASE, Amkor, SPIL) on process qualification and production ramp-up. Qualifications for the IC Packaging Engineer include: - years of hands-on experience in advanced semiconductor packaging and interconnect processes. -Proven expertise in CoWoS / FOCoS (highly preferred), or FOWLP; familiarity with EMIB, InFO, and advanced 2.5D/3D integration technologies is a plus. -Strong knowledge of thermal management, reliability testing, and signal/power integrity challenges. -Excellent analytical and problem-solving skills with a proactive and collaborative mindset. -Experience working with TSMC and leading OSATs. -Proficiency in Mandarin and English is preferred. -Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field. Compensation for the IC Packaging Engineer includes: -Salary range: $, - $, -Comprehensive benefit package: Medical, Dental, Vision, k match plus PTO, Sick leave as required by law, and Paid Holidays Keywords: principal packaging engineer, packaging, CoWoS, CoWoS packaging, semiconductor packaging, semiconductor, Chip-on-Wafer-on-Substrate, IC package development, IC packaging, chip performance, power efficiency, reliability, failure analysis, high-performance packaging, new product introduction, TSMC, ASE, FOCos, 2.5D/3D integration, datacenter, remote, onsite #LI-BH1 #LI-ONSITE This job opens for applications on 6//5. Applications for this job will be accepted for at least days from the posting date.