Join to apply for the Principal IC Packaging Engineer role at Piper Companies 12 hours ago Be among the first 25 applicants Join to apply for the Principal IC Packaging Engineer role at Piper Companies Get AI-powered advice on this job and more exclusive features. Piper Companies is seeking a Principal IC Packaging Engineer who will develop and refine Chip-on-Wafer-on-Substrate technology. The Packaging engineer will be onsite 5 days a week in Saratoga, CA.

Please double check you have the right level of experience and qualifications by reading the full overview of this opportunity below.

Requirements for the IC Packaging Engineer include:

Innovate and enhance CoWoS packaging processes to boost chip performance, power efficiency, and reliability. Collaborate with design, test, and manufacturing teams to ensure flawless chip-package integration. Lead failure analysis and drive yield improvements across packaging processes. Ensure CoWoS packaging meets all thermal, mechanical, and electrical performance standards. Support new product introduction (NPI) from initial prototyping to high-volume manufacturing. Partner with foundry and OSAT partners (e.g., TSMC, ASE, Amkor, SPIL) on process qualification and production ramp-up.

Qualifications for the IC Packaging Engineer include:

15 years of hands-on experience in advanced semiconductor packaging and interconnect processes. Proven expertise in CoWoS / FOCoS (highly preferred), or FOWLP; familiarity with EMIB, InFO, and advanced 2.5D/3D integration technologies is a plus. Strong knowledge of thermal management, reliability testing, and signal/power integrity challenges. Excellent analytical and problem-solving skills with a proactive and collaborative mindset. Experience working with TSMC and leading OSATs. Proficiency in Mandarin and English is preferred. Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.

Compensation for the IC Packaging Engineer includes:

Salary range: $210,000 - $300,000 Comprehensive benefit package: Medical, Dental, Vision, 401k match plus PTO, Sick leave as required by law, and Paid Holidays

Keywords: principal packaging engineer, packaging, CoWoS, CoWoS packaging, semiconductor packaging, semiconductor, Chip-on-Wafer-on-Substrate, IC package development, IC packaging, chip performance, power efficiency, reliability, failure analysis, high-performance packaging, new product introduction, TSMC, ASE, FOCos, 2.5D/3D integration, datacenter, remote, onsite

This job opens for applications on 7/18/2025. Applications for this job will be accepted for at least 30 days from the posting date.

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