Physical Design, Sr Principal Application Engineer
New Today
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Sr Principal Application Engineering (AE) - a blend of pre-sales, post-sales and design convergence in the netlist-GDS product space focusing on digital implementation and signoff.
As an expert Digital Implementation and Signoff Field Applications Engineering (AE) , you will work side-by-side with our leading-edge customers. With your expertise, you'll help them deploy Cadence’s market-leading technologies in Synthesis, P&R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn design concepts into reality. You will also work directly with the Cadence R&D group to drive the customer requirements and influence the direction of Cadence next-generation products and technologies
Primary focus will be for RTL-to-GDS digital implementation platform and signoff products (Genus, Joules, Innovus, Tempus, Quantus, Liberate) as well as industry shaping AI products (Cerebrus AI Studio, Cerebrus, CoPilot).
Job Requirements
Minimum
10+ years of industry Physical Design experience
BS degree Computer Science/Engineering, Electrical, Engineering, or related field
Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required
Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure
Experience with advanced nodes 10nm and below
Experience in scripting languages such as Tcl/Perl/Python is a must
Strong customer-facing communication and problem-solving skills
Strong personal drive for continuous learning and expanding professional skill sets
Strong verbal, written, and customer communication skills
Preferred
Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking
Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired
Experience with advanced nodes 5nm and below
We’re doing work that matters. Help us solve what others can’t.
- Location:
- San Jose