Design Verification Engineer

New Today

Typically requires minimum of 5-15 years of experience in System Verilog, UVM. Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering. Roles And Responsibilities:
Considering making an application for this job Check all the details in this job description, and then click on Apply. As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches. If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality. You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews. Required Technical And Professional Expertise: Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env. Understanding of verification tools like Simulator, Synthesis etc. Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc. Excellent written and verbal interpersonal skills Self-motivated and great teammate Seniority level Seniority levelMid-Senior level Employment type Employment typeFull-time Job function Job functionDesign, Information Technology, and Engineering IndustriesSemiconductor Manufacturing Referrals increase your chances of interviewing at Chiparama by 2x Get notified about new Design Verification Engineer jobs in San Francisco Bay Area . Sunnyvale, CA $111,000.00-$164,000.00 2 weeks ago Sunnyvale, CA $170,000.00-$240,000.00 1 week ago Fremont, CA $170,000.00-$240,000.00 2 weeks ago Sunnyvale, CA $139,000.00-$200,000.00 2 weeks ago Electrical Engineer - Electric Motors and Generators San Jose, CA $100,000.00-$130,000.00 2 weeks ago San Francisco Bay Area $110,000.00-$150,000.00 3 weeks ago Mountain View, CA $150,000.00-$230,000.00 1 month ago San Leandro, CA $75,000.00-$175,000.00 1 month ago Alameda County, CA $120,000.00-$160,000.00 3 weeks ago Newark, CA $110,000.00-$130,000.00 2 weeks ago San Francisco Bay Area $130,000.00-$150,000.00 3 weeks ago Hardware Engineer, Platforms, University Graduate Sunnyvale, CA $105,000.00-$151,000.00 2 days ago San Francisco, CA $140,000.00-$270,000.00 7 months ago Santa Rosa, CA $120,000.00-$160,000.00 2 days ago San Jose, CA $135,000.00-$175,000.00 1 week ago Atherton, CA $150,000.00-$200,000.00 5 months ago Fremont, CA $200,000.00-$210,000.00 1 week ago Fremont, CA $130,000.00-$180,000.00 3 days ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
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Location:
San Francisco, CA
Salary:
$250
Category:
Engineering

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