Join to apply for the ASIC/SoC Design Verification Engineer role at TetraMem - Accelerate The World Join to apply for the ASIC/SoC Design Verification Engineer role at TetraMem - Accelerate The World Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out Work with design engineers to debug and identify root causes of simulation failure Support test engineers for post-silicon validation Mentor and coach team members and junior engineers. Drive verification efficiency

Skills, Experience, Qualifications, If you have the right match for this opportunity, then make sure to apply today.

Responsibilities

Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out Work with design engineers to debug and identify root causes of simulation failure Support test engineers for post-silicon validation Mentor and coach team members and junior engineers. Drive verification efficiency

Requirements

MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core Experience in verifying designs at both of RTL level and post-P&R gate level Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

Experience in one or more of the following areas considered a strong plus:

Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators Experience in verifying mix-signal design and interface of digital and analog Experience of design verification for highspeed IO such as PCIE and DDR

Salary Range: $110,000 - $300,000 / yearSeniority level Seniority levelMid-Senior level Employment type Employment typeFull-time Job function Job functionStrategy/Planning and Information Technology IndustriesComputer Hardware Manufacturing Referrals increase your chances of interviewing at TetraMem - Accelerate The World by 2x Inferred from the description for this job Medical insurance Vision insurance 401(k) Get notified when a new job is posted. Sign in to set job alerts for “Design Verification Engineer” roles. Cupertino, CA $129,800.00-$212,800.00 10 hours ago Sunnyvale, CA $114,000.00-$166,000.00 13 hours ago San Jose, CA $136,000.00-$204,000.00 1 week ago San Jose, CA $136,000.00-$204,000.00 1 week ago Mountain View, CA $113,000.00-$161,000.00 2 weeks ago Sunnyvale, CA $114,000.00-$166,000.00 3 weeks ago Sunnyvale, CA $190,000.00-$200,000.00 7 hours ago Physical Design and Verification Engineer Sunnyvale, CA $142,000.00-$203,000.00 13 hours ago San Jose, CA $133,300.00-$186,800.00 1 week ago Design Verification Engineer (Fulltime role only) Mountain View, CA $107,900.00-$242,000.00 2 weeks ago CPU Verification Engineer (Multiple Locations) San Jose, CA $194,000.00-$410,000.00 2 weeks ago San Jose, CA $150,000.00-$275,000.00 2 weeks ago Sunnyvale, CA $173,000.00-$249,000.00 13 hours ago Cupertino, CA $104,000.00-$212,200.00 2 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

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