Join to apply for the ASIC RTL/SoC Design Engineer role at TetraMem - Accelerate The World Join to apply for the ASIC RTL/SoC Design Engineer role at TetraMem - Accelerate The World Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery

Experience, qualification, and soft skills, have you got everything required to succeed in this opportunity Find out below.

Responsibilities

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery

Requirements

MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design Experience with Verilog and system Verilog Experience with VCS, Verdi or other industry standard tools Experience with pre-layout simulation and post-layout simulation Understanding of the design flow. Ability to work with the backend team Familiarity with AMBA APB AXI Protocol Familiarity with RISC/Arm or other core architectures Ability to create innovative architecture and solutions to customer requirements Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.

Experience in one or more of the following areas considered a strong plus:

FPGA/ASIC design of image processing systems Working knowledge of SoC architecture such as CPU, GPU or accelerators Familiarity with: UVM, place-and-route, STA, EM/IR/Power

Salary Range: $110,000 - $300,000 / yearSeniority level Seniority levelMid-Senior level Employment type Employment typeFull-time Job function Job functionStrategy/Planning and Information Technology IndustriesComputer Hardware Manufacturing Referrals increase your chances of interviewing at TetraMem - Accelerate The World by 2x Get notified about new System-on-Chip Design Engineer jobs in San Jose, CA . Sunnyvale, CA $114,000.00-$166,000.00 23 hours ago Physical Design Engineer - Synthesis, PNR, STA San Jose, CA $90,000.00-$110,000.00 1 month ago Sunnyvale, CA $114,000.00-$166,000.00 4 days ago Sunnyvale, CA $142,000.00-$203,000.00 2 days ago Menlo Park, CA $212,000.00-$291,000.00 2 weeks ago Sunnyvale, CA $212,000.00-$291,000.00 2 weeks ago Sunnyvale, CA $173,000.00-$249,000.00 3 days ago San Jose, CA $152,400.00-$221,800.00 2 weeks ago Mountain View, CA $120,000.00-$400,000.00 9 months ago San Jose, CA $135,800.00-$193,400.00 2 weeks ago Sunnyvale, CA $114,000.00-$166,000.00 1 week ago Sunnyvale, CA $156,000.00-$229,000.00 2 weeks ago CPU Physical Design – Low Power Signoff Engineer San Jose, CA $152,400.00-$221,800.00 2 weeks ago Physical Design and Verification Engineer San Jose, CA $120,000.00-$136,000.00 2 weeks ago Santa Clara, CA $108,000.00-$212,750.00 5 days ago Physical Design Engineer - Multiple Levels Sunnyvale, CA $212,000.00-$291,000.00 3 days ago Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago ASIC/SOC Silicon Physical Design Engineer Mountain View, CA $120,000.00-$400,000.00 9 months ago Mountain View, CA $120,000.00-$400,000.00 9 months ago Low Power ASIC Engineer - New College Grad 2025 Sunnyvale, CA $142,000.00-$203,000.00 1 week ago Sunnyvale, CA $212,000.00-$291,000.00 2 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

#J-18808-Ljbffr