ASIC Engineer, Physical Design, Sunnyvale, CA, United States

ASIC Engineer, Physical Design

New Yesterday

Summary: Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in physical design from RTL to GDSII in low power and high-performance designs to build efficient System on Chip (SoC) and IP for data center applications. Required Skills: ASIC Engineer, Physical Design Responsibilities: Develop and own physical design implementation of multi-hierarchy SOCs optimized for Perf/W, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes

Contribute to Architecture decisions for physical design, floorplanning, partitioning, clocking, etc. Work with the Design team to understand partition architecture and drive physical aspects early in the design cycle

Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution

Deliver physical design of an end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs

Interface with the RTL design team to drive design modifications to resolve congestion/timing issues and implement functional ECO’s

Use EDA tool-based programming and scripting techniques to automate and develop methodologies to improve throughput and quality

Interact with EDA tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions

Minimum Qualifications: Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

12+ years of experience in interpersonal, teamwork, and demonstrated experience communicating and interfacing with cross-functional teams, IP, and EDA vendors

Experience in physical design and timing closure

Knowledge of RTL2GDSII flow and experience with design tape-outs in 5nm or below process technologies

Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Redhawk/Voltus, or Calibre

Hands-on experience in SoC floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs

Knowledge of geometry/process/device technology implications on physical design

Experience with large/disaggregated SOC designs (>100M gates) with frequencies over 1GHZ

Programming/scripting skills: TCL, Python, Perl or Shell

Preferred Qualifications: Preferred Qualifications: Experience in full chip floor planning, partitioning, budgeting, and power grid planning

Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge

Experience in planning, implementing, and analyzing high-speed clock distribution networks. Experience with alternate strategies for clock distribution, including standard trees, mesh, H-Tree, and clock power reduction techniques

Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions

Experience in the physical design of data-path intensive designs

Experience in the 3D-IC technology, methodology, and advanced packaging

Experience in validating Power Distribution Network (PDN), IR/EM, Thermals for 3D-IC

Public Compensation: $212,000/year to $291,000/year + bonus + equity + benefits Industry: Internet Equal Opportunity: Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

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Location:: Sunnyvale, CA, United States
Category:: Engineering

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