Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.

Job Description:

As an Astera Labs Tech Lead Firmware Engineer, you will be designing and developing Firmware for enabling DDR technologies for future looking products defined by Astera Labs CXL memory solutions.

Basic qualifications:

Bachelor's in Electrical engineering / Electronics / Computer Science or related fields. Required experience : 5+ years of experience in developing Firmware using C in Embedded environments. Good knowledge in DDR Technology internals (DDR Training, DDR RAS, PMIC, RCD etc.) Ability to debug DDR related issues. Preferred experience: Post-Silicon bring up and validation of DDR memory interfaces Experience working with cross-functional teams and partners. Pre-Silicon DDR bring up experience is a plus Experience with RDIMMs, DDR controller/PHY tuning is a plus Knowledge of Server memory performance and stability tuning for latency and bandwidth is a plus

The base salary range is 140,000.00 USD - 200,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.