About us:

Aeva's mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.

Role Overview:

As a senior member of Physical Design Team at Aeva, you will be working on all aspects (RTL2GDS) of Physical Implementation of our next generation LiDar SoCs.

What you'll do As a Physical Design Engineer, you will be responsible for performing Synthesis, Floorplanning, Clock/Power Planning, Timing Analysis, Power Integrity, ECOs, Library/tool flow setup, design QA, Develop Tapeout checklists, flow automation, etc on a high-performance LiDAR processing chip. You will work closely with logic designers and back-end engineers to ensure high-quality netlist handoff and minimize iteration in the implementation process. What you'll have 12+ years of experience in Physical Implementation of high-performance SoCs at advanced nodes. Broad knowledge of advanced Synthesis techniques, Place and Route, Floorplanning, Top-Level Integration, Global/Local clock distribution, STA-based timing convergence, constraints management, Power Distribution Network development and analysis, low power implementation techniques, Logic Equivalence check, Physical design verification and automated ECO flows. Experience in developing and analyzing Power Distribution Networks at Block/Chip-Level Experience in Implementing complex clock structures in a SoC Experience in developing and implementing IO pad ring, RDL routing, etc In-depth knowledge of EDA tools used in Physical Design, particularly Cadence. Scripting expertise in Python/PERL, TCL, etc Recent tapeouts in advanced technology nodes. Desire to learn and implement groundbreaking new hardware technology Nice to have High-Performance CPU or Communication chip background Experience in integrating High-Performance analog design in a high-performance digital chip Experience in constraints debugging and work with Designers to resolve timing issues