PLEASE NOTE THIS ROLE WILL REQUIRE 5 DAYS PER WEEK ONSITE IN OUR FARNBOROUGH OFFICE We are searching for a Principal level radio frequency integrated circuit (RFIC)/Analogue design engineer to join a strong group of RFIC designers to help lead Qualcomm in the development of RF transceivers to address the IoT market. Working within a dynamic design team you will participate in the development of next generation RFIC products in the IoT wireless space. RESPONSIBILITIES: Specify, design and verify key circuits and sub-systems of integrated RF transceivers Work closely with other teams to facilitate the design and production process, e.g. Software, Signal Processing, Product Integration, Sales & Marketing Provide broad technical expertise and mentor junior engineers within the team REQUIRED EXPERIENCE: Engineering degree in a relevant discipline. BSc, MSc or equivalent 10 to 15 years’ experience of relevant IC development Fluent English speaker Recent successful RFIC/analogue project contributions on highly integrated RF transceivers, ideally related to broadband wireless communication systems, e.g. WiFi or LTE, on a nanometer scale RF-CMOS technology Understanding of low power/low noise design techniques for analogue and RF Knowledge of Design for Manufacture considerations on cutting edge processes Full appreciation of RF and analogue layout techniques REQUIRED DETAILED KNOWLEDGE: Proficiency in Cadence and/or Mentor frontend and backend tools are absolutely required Familiarity with RF lab equipment such as signal generators, spectrum analyzers, and vector signal analyzers is required PREFERRED DETAILED KNOWLEDGE: Wideband IF circuits for broadband transceivers (including high-speed operational amplifiers and filters) Multi-band RF circuit design in the 700MHz to 7GHz range Design experience with circuits such as amplifiers, low power oscillators, low drop out regulators, data converters, high precision biasing techniques, etc. RFIC system and architecture design, ideally for OFDM applications RFIC sub-system and block level definition & specification ADDITIONAL USEFUL EXPERIENCE: System simulation Integrated single chip RF + digital baseband projects Top level chip simulation and functional verification Analogue behavioral language modeling (e.g. Verilog-AMS) Mixed-mode simulation environments (e.g. mixed Verilog and device level) Direct conversion Rx and Tx architectures and associated considerations DFT and BIST for analogue and RF circuits Silicon test and de-bugging KEY WORDS: CMOS IoT RF and analogue RFIC Designer Cadence +10 years’ experience in RFIC design BSc, MSc

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