SoC Physical Design Engineer, Implementation SoC Physical Design Engineer, Implementation 5 days ago Be among the first 25 applicants Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience in Physical Design. Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC). Experience in high performance synthesis, PnR, sign-off convergence, including STA and sign-off.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience in Physical Design. Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC). Experience in high performance synthesis, PnR, sign-off convergence, including STA and sign-off.

Preferred qualifications:

Experience with ASIC design flows and methodology of Physical design. Experience in low power design Implementation including UPF/CPF, multi-voltage domains, power gating. Experience with scripting languages such as TCI, or Perl. Knowledge of computer architecture, Verilog or SystemVerilog. Understanding of Circuit design, device physics and deep sub-micron technology.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

Define and implement innovative methodology schemes to improve Performance, Area and Power. Develop all aspects of ASIC RTL2GDS implementation for designs. Manage physical implementation for partitions. Work with cross-functional teams to deliver results.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form. Seniority level Seniority level Not Applicable Employment type Employment type Full-time Job function Job function Other, Information Technology, and Engineering Industries Information Services and Technology, Information and Internet Referrals increase your chances of interviewing at Google by 2x Get notified about new Physical Design Engineer jobs in Mountain View, CA . Physical Design Engineer, Custom Datapath Sunnyvale, CA $183,000.00-$271,000.00 2 weeks ago Physical Design and Verification Engineer Sunnyvale, CA $142,000.00-$203,000.00 3 weeks ago ASIC/SOC Silicon Physical Design Engineer Mountain View, CA $120,000.00-$400,000.00 8 months ago Mountain View, CA $156,000.00-$229,000.00 12 hours ago San Jose, CA $150,000.00-$275,000.00 6 days ago Cupertino, CA $104,000.00-$212,200.00 9 hours ago Santa Clara, CA $108,000.00-$212,750.00 8 hours ago Physical Design Engineer (Place & Route) CPU Physical Design – Low Power Signoff Engineer SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA $130,000.00-$155,000.00 2 weeks ago Fremont, CA $115,000.00-$120,000.00 1 week ago ASIC Physical Design Engineer, Annapurna Labs San Francisco Bay Area $145,000.00-$225,000.00 4 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

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