Silicon Packaging Engineer
5 Days Old
Direct message the job poster from Vivid Technology
Make your application after reading the following skill and qualification requirements for this position.
Fresh off a successful funding round, this well-capitalized (Series B) start-up is pioneering a new category of high-resolution perception sensing technology for ADAS and autonomous driving.
Seeking an IC Packaging Engineer who will own the development and delivery of advanced packaging solutions for THz system RFIC & SoC applications. This is a high-impact role that combines technical leadership, hands-on design, and vendor management to bring cutting-edge multi-chip packages into production.
Responsibilities
Technical leadership, guiding the design and execution of advanced IC packages for multi-chip RFIC/SoC integration.
Develop 2.5D packages with UCIe chip-to-chip interconnects and interposer-based solutions.
Work on single-sided and double-sided RDL designs and on-package RF antenna structures.
Co-optimize package designs for signal integrity, thermal, and mechanical performance in collaboration with RFIC, digital, and system engineers.
Drive material selection, DFM, and reliability qualification to meet automotive-grade requirements (AEC-Q).
Perform stress, warpage, and thermal simulations using tools such as ANSYS.
Maintain and leverage relationships with OSATs, substrate suppliers, and ecosystem partners to accelerate development.
Create and review mechanical drawings, stack-ups, and layout constraints.
Lead failure analysis and root cause investigations for packaging and reliability issues.
Contribute to the packaging roadmap and scalability plan for automotive volume production.
Key Qualifications
10+ years of experience in IC packaging design and development, including leadership responsibilities.
Proven track record with multi-chip packages, digital + RF integration, and automotive applications.
Deep knowledge of UCIe interconnects, interposers, and advanced packaging architectures.
Experience with RF antenna integration in package designs.
Proficient in Flip-Chip, Fan-Out, 2.5D integration, and heterogeneous system-in-package solutions.
Strong understanding of signal integrity, mechanical stress, thermal management, and reliability analysis.
Established network with packaging vendors and OSATs.
M.S. or Ph.D. in Mechanical Engineering, Materials Science, Electrical Engineering, or related field.
Excellent communication skills and ability to thrive in a fast-paced start-up environment.
Location
Hybrid work from one of the office locations:
Bay Area, CA
Seniority level Seniority levelMid-Senior level
Employment type Employment typeFull-time
Job function Job functionEngineering, Science, and Project Management
IndustriesSemiconductor Manufacturing, Motor Vehicle Manufacturing, and Appliances, Electrical, and Electronics Manufacturing
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- Location:
- San Francisco, CA
- Salary:
- $200
- Category:
- Engineering