Location: Hybrid – Santa Clara, CA or Austin, TX Type: Full-Time | Salary: $150K–$250K + Competitive Equity Visa Sponsorship: H-1B, O-1, OPT Available About the Opportunity Initio Capital is hiring a Design Verification Engineer on behalf of one of the most ambitious chip startups in the U.S.—a stealth-mode team redefining the future of AI and analytics acceleration . Backed by top-tier investors and built around a seasoned team from Apple, Intel, and Nvidia, this company is designing RISC-V–based silicon with tightly integrated AI acceleration and custom workloads in mind. This is an opportunity to work on deeply complex verification challenges that impact compute performance, efficiency, and reliability at the foundational layer of modern infrastructure. About the Role As a Silicon Verification Engineer , you'll take ownership of top-level verification for the company’s AI/analytics accelerator. You'll define and implement verification strategies, write test plans, build emulation-friendly testbenches, and partner with software and silicon teams to enable end-to-end validation. This role offers the chance to shape product and verification flow in a high-autonomy environment. What You’ll Do Develop verification strategy and own DV execution for complex accelerator subsystems

Write and maintain testbenches in SystemVerilog, C++, and Python

Create coverage-driven and directed/random tests for full-chip and subsystem validation

Collaborate with software, firmware, and architecture teams for co-simulation

Build infrastructure for emulation, simulation, and hardware bring-up

Deliver high-quality silicon verification aligned with aggressive execution timelines

What We’re Looking For 5+ years of hands-on design verification (DV) experience

MS or PhD in Electrical Engineering, Computer Engineering, or related field

Strong SystemVerilog, C++, and/or Python development skills

Deep understanding of computer architecture, SoC design, and memory/cache subsystems

Proven experience verifying CPUs, GPUs, or custom accelerators

Familiarity with industry-standard DV methodologies (UVM, formal, coverage-driven, etc.)

Bonus Points Experience enabling HW/SW co-simulation or working on firmware test coverage

Past contributions to hardware/software co-design workflows

Previous experience at early-stage silicon or systems startups

Passion for AI/ML workloads, compute acceleration, or chip performance optimization

Compensation & Perks Salary: $150K – $250K

Equity: Meaningful early-stage grant

Hybrid in Santa Clara, CA or Austin, TX

H-1B, O-1, OPT sponsorship available

Collaborate with industry leaders from the most respected names in semiconductors

Work on a moonshot AI-silicon vision with deep technical impact and upside

This is the rare chance to define the performance boundaries of next- AI chips from the ground up. Apply now to be considered for this high-impact role.

#J-18808-Ljbffr