Duties: • Contribute to the development of efficient Architectures and contribute to ASIC digital Architecture, design and verification

• IPs integration

• Understand Design for Verification concepts

• Drive the top-level μArchitecture definition and develop the necessary RTL

• Drive the chip-level integration, verification plan development and verification

• Supervise the RTL-to-GDS flow and assist with synthesis and timing closure

• Support the test program development, chip validation and chip life until production maturity

• Work with FPGA engineers to perform early prototyping

• Support hand-off and integration of blocks into larger SOC environments

• Assist with Algorithm analysis, verification and improvement

• Contribute to ASIC digital architecture, design and verification

Skills

Must Have:

• + years of experience as a Digital Design Engineer and/or a Chip Lead

• Experience in RTL coding, synthesis and/or SoC Integration

• Experience in digital design Architecture

• BS Electrical Engineering/Computer Science or equivalent experience

• Experience with UPF based simulation flow

• System Verilog OVM/UVM experience

• Tcl and Python (or similar) scripting experience

• Experience in SoC integration and ASIC architecture

Wish List/ Nice to Have:

• Experience in DFT/Testability requirement and test program definition

• Experience using High Speed interfaces like PCIe, USB, MIPI

• FPGA design

• Tensilica DSP, TIE, CNN, fixed point, floating point, python.

• Experience with Power Aware GLS flow

• MSEE/CS or equivalent experience

Years of Experience: + years of experience as a Digital Design Engineer and/or a Chip Lead

Degrees/Certifications Required:

Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science

Master's Degree preferred but not required

Candidate Disqualifiers

Are there any types of candidate profiles or skills that may not be the right fit for this team? Needs to have Strong System Verilog OVM/UVM experience EEO: “