About Analog Devices Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and. Summary In this position, you will join a team of expert analog/mixed-signal/digital designers and play a leading technical role as a SerDes Designer and System Architect for low power, high-speed SerDes IPs. You will be involved in the design, verification, and implementation of advanced signal processing algorithms for high speed SerDes. The types of algorithms that will be implemented include adaptive equalizers, digital filters, and different types of analog-circuit-nonideality compensation for both binary and higher-order PAM modulations. Key Qualifications Master’s degree with 7+ years of experience or Ph.D. with 4+ years of experience is typical Digital signal processing experience and understanding Design and verification experience with complex digital designs using Verilog/SystemVerilog Experience architecting and planning designs at the system level, taking conceptual product definitions and translating to design implementations Knowledge of advanced mixed-signal SerDes transceiver architectures Excellent knowledge in communication theory Excellent knowledge in Matlab/Simulink and SystemVerilog real number modeling Understanding of signal-integrity concepts, electrical channel modeling, clock and data recovery concepts, LMS adaptation algorithms Working knowledge of analog circuit design trade-offs Familiarity with lab measurements and silicon debug Familiarity with C/C++ programming is a plus Job Description Define block and system level architectures for next generation SerDes PHYs Write block specifications and track execution at circuit-design level Develop and maintain end-to-end Matlab/Simulink system models Develop and run block-level DSP simulation testbenches. Apply this to system-level simulations to evaluate architectural tradeoffs. Use Verilog/SystemVerilog to design digital signal processing blocks Develop algorithms for adaptation and calibration of mixed-signal circuit blocks Communicate effectively with circuit-designers and verification engineers to incorporate circuit nonidealities in system models Work across the digital/analog boundary, including support of mixed-signal simulations and real number modeling Work with technical leads and across multiple disciplines, including design, verification, test, product definition Minimum Qualifications Masters of Science plus 7 years of relevant experience or Ph.D. plus 4 years of relevant experience.

Education Masters Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $141,075 to $211,613. Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.

This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time , and other benefits.