Advantest is seeking an experienced and visionary Senior Semiconductor Processing Engineer to serve as a key technical leader and strategic liaison in collaborative R&D projects with leading-edge wafer fabrication partners. This individual will bring deep expertise in front-end wafer processing and fabrication technologies, a strong track record of innovation and execution, and the executive presence to lead strategic conversations across customers, partners, and internal stakeholders.The successful candidate will guide Advantest's efforts in engaging with semiconductor ecosystem partners to co-develop next-generation solutions in process integration, metrology, materials engineering, and yield optimization. The ideal candidate comes with a deep front-end fab pedigree and a passion for solving hard semiconductor process problems.This is a unique opportunity to shape the future of semiconductor processing at the intersection of innovation and collaboration. Join Advantest to lead groundbreaking work that bridges fabs, toolmakers, and test ecosystemsResponsibilities :Technical Strategy & Program Leadership :Lead strategic planning, ideation, and execution of joint R&D initiatives in wafer process engineering.Serve as the primary technical voice for all things related to front-end fab technology and process trends.Collaborate with partner organizations to define, negotiate, and execute collaborative development agreements.Translate industry needs into internal innovation roadmaps.Semiconductor Process Expertise :Provide deep knowledge of process modules (e.g., etch, deposition, lithography, CMP, thermal treatment, cleaning, metrology) across logic, memory, and advanced packaging nodes.Expertise in advanced packaging processes, esp. advanced substrates and assembliesBroad process integration experience.Expertise in mapping advanced packaging defects into tester / metrology solutions, esp. for substrate level defect inspection.Identify critical challenges in semiconductor scaling and yield, and champion novel engineering approaches.Evaluate tool capabilities, process flows, and integration schemes for collaborative pilot development.Deep understanding of ion diffusion simulation.Expertise in forming processes and their impact on stable, uniform SET / RESET cycling in memory devices.Modeling and characterization of nanoelectronic non-volatile memory devices, including charge transport and degradation in high-k materials.Cross-functional Collaboration :Partner closely with design, fabrication, test, and product engineering teams to ensure full lifecycle coverage.Act as the bridge between customer technical experts and Advantest's engineering teams.Drive knowledge transfer and technical communication internally to align development resources.Lead executive-level and technical discussions with semiconductor customers, consortia, and partners.Develop and manage external collaborations that support Advantest's strategic semiconductor innovation roadmap.Represent Advantest at industry events, conferences, and technical working groups.Identify patentable innovations and support IP development efforts.Track industry and academic advancements to guide internal innovation.Requirements :Ph.D. or Master's degree in Materials Science, Electrical Engineering, Chemical Engineering, or a related field.12+ years of experience in front-end wafer processing in semiconductor R&D or high-volume manufacturing.Proven ability to lead complex cross-company technical initiatives.Deep technical fluency across fab tools, process flows, integration challenges, and yield analysis.Strong executive presence and excellent written / oral communication skills.Demonstrated creativity in addressing hard technical and strategic problems.Strong network in the semiconductor ecosystem, including relationships with fab tool vendors, consortia, and foundries.Additional Skills Preferred (but not required) :Experience in technical leadership roles within a semiconductor equipment or device company.Participation in industry standards bodies or consortia (e.g., SEMI, IRDS).Previous experience in joint development or technology partnership programs.Strong understanding of AI / ML applications in fab process optimization.Experience in data analytics, AI framework, and real-time feedforward / feedback process controlFamiliarity with process control, defect inspection, or metrology workflows.Experience with academic / industrial joint research programs.Development experience with planar CMOS technologies including 28nm and 22nm FDSOI.FinFET process development experience down to 14nm.Demonstrated history of process / device development for 90nm to 40nm CMOS nodes.Simulation and integration of advanced transistor nodes including 65nm SOI, 45nm strained Si on relaxed SiGe, and the 32nm Node. #J-18808-Ljbffr