Senior Digital Verification Engineer

The full job description covers all associated skills, previous experience, and any qualifications that applicants are expected to have. We're looking for a digital verification engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions. Job title and responsibilities are commensurate with experience. Responsibilities: Continuously improve verification flow with emphasis on reusability across projects. Serve as a significant individual contributor. Manage and direct other DV engineers. Provide best-in-class DV at both IP and SOC levels. Create and review test plans through peer reviews. Track progress using quantitative metrics. Make go/no-go decisions for tape-outs. Requirements: Proficiency in verification test planning and test bench architecture. Knowledge of common DV techniques such as assertions, SystemVerilog, OVM/UVM, constrained random, and coverage (code/functional/assertion). Strong knowledge of Verilog or VHDL, C. Experience with scripting and automation; capable of setting up and maintaining automated regressions. Ability to interpret design specifications and develop test plans; willingness to debug designs and collaborate with logic designers. Ability to run and debug gate-level simulations. BSc or MSc in EE or equivalent, with 10+ years of experience. Nice to Have: DV experience with low-power design techniques, particularly power islands and UPF. Experience developing C-based tests for ARM-M processors. Understanding of secure/non-secure spaces and dynamic clock frequency switching. Knowledge of wireless communications, especially BLE protocol.

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