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Making sure you fit the guidelines as an applicant for this role is essential, please read the below carefully. Get AI-powered advice on this job and more exclusive features. Direct message the job poster from EDA CAREERS, (Technology Futures Inc). President at EDA-CAREERS and TECHNOLOGY FUTURES Inc. YOU MUST HAVE WORKING KNOWLEDGE OF EDA tools and Semiconductors! PLEASE HAVE EDA/SEMICONDUTOR EXPERIENCE WHEN APPLYING! This company is reinventing semiconductor with founders that are the leading experts in AI and chip design and are working with top-20 semiconductor companies, major cloud providers, and next-generation hardware startups. Their design and verification is performed through agentic AI workflows and their AI-powered platform accelerates RTL design, verification, and simulation, enabling engineers to achieve unprecedented productivity and correctness. This is a chance to work at the frontier of AI and semiconductor design and to collaborate with a world-class team spanning AI, systems, and EDA. Your work will help shape a foundational shift in how chips are built. They are seeking highly capable Senior Design and Verification Engineers to work on their core product and research team. In this role, you will work side-by-side with the AI engineering and research groups to build cutting-edge agentic AI systems for EDA. Your deep domain expertise in RTL design and functional verification will shape how AI systems reason about complex hardware workflows—from architecture specification through testbench validation. You will play a central role in teaching our AI how engineers think and work, ensuring our solutions integrate naturally into real-world design environments. Key Responsibilities: Collaborate with AI engineers to model and codify chip design and verification workflows. Design, implement, and debug RTL designs and SystemVerilog/UVM testbenches used in training and validating AI agents. Provide deep domain expertise to help AI agents interpret specifications, generate RTL code, and understand verification coverage. Build reusable examples, design patterns, and edge cases to train and evaluate generative and agentic AI models. Support benchmarking and evaluation of AI-assisted design and verification productivity across realistic chip development tasks. Work closely with customers, product, and research teams to translate engineering pain points into automated AI workflows. Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related field. 5+ years of experience in RTL design, functional verification, and/or architecture-level modeling. Proficiency with Verilog/SystemVerilog, UVM, and simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa). Experience designing and verifying complex subsystems or SoCs, preferably in production or research tapeouts. Familiarity with lint, CDC, formal, coverage analysis, and synthesis flows. Interest or experience in AI/ML, especially AI-assisted engineering tools, a plus. Strong collaboration skills; a passion for enabling the next gen EDA workflows. Competitive salary, meaningful equity, benefits, and growth opportunities. To learn more about this and other openings, contact Mark Gilbert anytime by email, mark@eda-careers.com or call 305-598-2222x3. Please include your resume so we can have a more precise conversation. Seniority level Seniority levelMid-Senior level Employment type Employment typeFull-time Job function Job functionInformation Technology, Engineering, and Quality Assurance IndustriesSemiconductor Manufacturing, Computers and Electronics Manufacturing, and Computer Hardware Manufacturing Referrals increase your chances of interviewing at EDA CAREERS, (Technology Futures Inc). by 2x Inferred from the description for this job Medical insurance Vision insurance 401(k) Get notified about new Design Verification Engineer jobs in San Francisco Bay Area . Sunnyvale, CA $114,000.00-$166,000.00 1 day ago San Jose, CA $136,000.00-$204,000.00 1 week ago Sunnyvale, CA $114,000.00-$166,000.00 5 hours ago San Jose, CA $136,000.00-$204,000.00 1 week ago Mountain View, CA $113,000.00-$161,000.00 2 weeks ago Cupertino, CA $104,000.00-$212,200.00 2 weeks ago Sunnyvale, CA $142,000.00-$203,000.00 1 day ago Sunnyvale, CA $190,000.00-$200,000.00 23 hours ago CPU Verification Engineer (Multiple Locations)Physical Design and Verification EngineerSenior Mechanical Design Verification Test Engineer Santa Clara, CA $108,000.00-$212,750.00 3 days ago Sunnyvale, CA $173,000.00-$249,000.00 1 day ago San Jose, CA $133,300.00-$186,800.00 1 week ago San Jose, CA $194,000.00-$410,000.00 2 weeks ago Santa Clara, CA $86,000.00-$123,500.00 3 days ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

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