Principal Design Engineer
New Today
Overview
Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.
We are looking for a Principal Design Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment.
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Qualifications
Required Qualifications
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
7+ years expertise in high-speed digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog or similar, PPA optimization, and design verification collaboration
Previous experience in the following:High-speed/high-performance data path design and optimizationArtificial Intelligence (AI), Machine Learning (ML), and/or floating-point compute unitsComplex Intellectual Property (IP) development in Intra-chip high-speed data transmission fabric, cache memory hierarchies, near-memory computation solutions, processor/ accelerators
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications
Established reputation as an expert in one or more domains of high-speed silicon design
Track record of successful tape outs in deep sub-micron technologies
Scripting language such as Python or Perl
Substantial background in debugging designs as well as simulation environment
Knowledge of verification principles, testbenches, UVM, and coverage
Working knowledge of writing assertions, coverage and formal verification
Communication skills, self-motivation, and ability to collaborate with larger teams within Microsoft
System software/firmware/hardware interactions and optimization
Experience in Sub-system and SoC integration
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
Microsoft will accept applications for the role until August 6th, 2025.
#AHSI #SCHIE
Responsibilities
Establish yourself as an integral member of a digital logic design team for the development of AI components with focus on micro-architectural based functions and features
Be responsible forMicroarchitecture and Logic design/Register Transfer Level (RTL) entryPower, performance, area (PPA) closure of high-performance digital designDesign quality: including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc.Silicon validation
Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent
Interface with architecture, physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design
Provide technical leadership through mentorship and teamwork
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.Industry leading healthcareEducational resourcesDiscounts on products and servicesSavings and investmentsMaternity and paternity leaveGenerous time awayGiving programsOpportunities to network and connect
- Location:
- Austin
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