Physical Design Engineer

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Job Title: Physical Design Engineer Location: USA Experience: 6+ Years Job Description: We are actively hiring Physical Design Engineers for leading semiconductor clients across the U.S. The ideal candidate will be responsible for full-chip or block-level implementation of complex SoCs/ASICs using advanced process nodes (7nm, 5nm, 3nm). This is an excellent opportunity to work on cutting-edge technologies in a highly collaborative environment. Key Responsibilities: Execute RTL to GDSII implementation for high-performance SoCs and ASICs. Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical sign-off. Conduct static timing analysis (STA), IR/EM analysis, and physical verification (LVS/DRC). Optimize designs for power, performance, and area (PPA). Collaborate with RTL, DFT, and architecture teams to ensure seamless integration and convergence. Participate in tape-out activities and support post-silicon validation. Required Skills: Minimum 6 years of hands-on experience in physical design. Proficiency with tools like Cadence Innovus, Synopsys ICC2, PrimeTime, RedHawk, and Calibre. Strong expertise in STA, IR/EM, and sign-off methodologies. Experience with advanced process nodes (7nm, 5nm, or 3nm). Solid understanding of low-power design techniques (UPF/CPF). Scripting proficiency in TCL, Perl, or Python. Experience in hierarchical and flat physical design implementation.
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Location:
NJ, United States

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