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Role: CAD/EDA – Silicon Design/Verification Infrastructure Engineer

Location: Santa Clara, CA (Onsite)

Interview: Phone/Skype 

Job Type: Contract 

We’re hiring a skilled engineer to support advanced SoC/IP design and verification infrastructure. Candidates should bring hands-on experience with #SystemVerilog #UVM #Python #Perl #TCL #Synopsys #Cadence #EDA #LinuxDevelopment and integration testing for multicore architectures.

All your information will be kept confidential according to EEO guidelines.